copyright ? anpec electronics corp. rev.p.1 - mar., 2001 APW7025 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. advanced pwm and dual linear power control features general description ? ? ? ? ? 3 regulated voltage are provided ? ? ? ? ? switching power for vtt(1.25v) ? ? ? ? ? linear1 regulator for fbvddq(2.5v) ? ? ? ? ? linear2 regulator for nvvdd(2.05v) ? ? ? ? ? simple single-loop control design ? ? ? ? ? voltage-mode pwm control ? ? ? ? ? excellent output voltage regulation ? ? ? ? ? pwm output 1% ? ? ? ? ? linear output 3% ? ? ? ? ? fast transient response ? ? ? ? ? high-bandwidth error amplifier ? ? ? ? ? full 0% to 100% duty ratio ? ? ? ? ? power-good output voltage monitor ? ? ? ? ? over-voltage and over-current fault monitors ? ? ? ? ? small converter size ? ? ? ? ? constant frequency operation(200khz) ? ? ? ? ? programmable oscillator from 50khz to 1mhz ? ? ? ? ? reduce external component count ? ? ? ? ? motherboard power regulation for computers ? ? ? ? ? low-voltage distributed power supplies ? ? ? ? ? vga card power regulation applications the APW7025 integrates a pwm controller and dual linear controller, as well as the monitoring and pro- tection functions into a single package , which pro- vides three controlled power outputs with over-volt- age and over-current protections. the pwm control- ler regulates the ddr reference voltage with a syn- chronous-rectified buck converter. the linear control- ler regulates power for microprocessor core voltage and memory voltage. the precision reference and voltage-mode pwm control provide 2% static regulation. the linear controller drives an external n-channel mosfet to provide adjustable voltage. the APW7025 monitors all the output voltages , and a single power good signal is issued when the pwm voltage is within 10% of the 1.25v setting and the other output levels are above their under-voltage thresholds. additional built-in over-voltage protec- tion for the pwm output uses the lower mosfet to prevent output voltages above 115% of the 1.25v setting. the pwm over-current function monitors the output current by using the voltage drop across the upper mosfet?s r ds(on) , eliminating the need for a current sensing resistor. pin description vcc drive2 nc nc lgate ocset vsen1 nc nc pgood vsen2 pgnd fb comp vsen3 gnd 1 2 3 4 5 6 7 8 12 11 ugate 10 9 16 15 14 13 17 18 19 20 24 23 22 21 vaux drive3 phase nc ss fault nc sop24
copyright ? anpec electronics corp. rev. p.1 - mar., 2001 APW7025 www.anpec.com.tw 2 ordering information APW7025 package code k : sop - 24 temp. range c : 0 to 70 c handling code tu : tube tr : tape & reel handling code temp. range package code block diagram absolute maximum ratings pgood power-on reset (por) vcc 200 a 1.10 soft start & fault logic + - gate control + - pwm comp1 synch drive ov ugate phase v cc lgate pgnd comp fb ss ocset vsen1 error amp1 pwm1 vcc inhibit oc1 driver1 vaux luv linear under- voltage drive3 - + + - - + + - + - + - oscillator fault 0.90 1.15 v cc 4.5v 28 a fault inhibit vaux drive2 vsen2 gnd vsen3 1.26v + - 0.75 + - + - 1.5v + - 1.25v + - symbol parameter rating unit v cc supply voltage 15 v v i , v o input , output or i/o voltage gnd -0.3 v to v cc +0.3 v t a operating ambient temperature range 0 to 70 c t j junction temperature range 0 to 125 c t stg storage temperature range -65 to +150 c t s soldering temperature 300 ,10 seconds c
copyright ? anpec electronics corp. rev. p.1 - mar., 2001 APW7025 www.anpec.com.tw 3 electrical characteristics thermal characteristics symbol parameter value unit r ja thermal resistance in free air soic soic (with 3in 2 of copper) 75 65 c/w (recommended operating conditions , unless otherwise noted) refer to block and simplified power system diagrams , and typical application schematic APW7025 symbol parameter test conditions min. typ. max. unit v cc supply current i cc nominal supply current ugate, lgate, drive2, drive3 open 9ma power-on reset rising vcc threshold vocset=4.5v 10.4 v falling vcc threshold vocset=4.5v 8.2 v rising vaux threshold vocset=4.5v 2.5 v vaux threshold hysteresis vocset=4.5v 0.5 v rising v ocset threshold 1.26 v oscillator f ocs free running frequency rt= open 185 200 215 khz ? v osc ramp amplitude rt= open 1.9 v p-p dac and bandgap reference dac voltage accuracy -1.0 +1.0 % v bg bandgap reference voltage 1.265 v bandgap reference tolerance -2.5 +2.5 % linear regulators (out2, out3) regulation (all linears) 3 % output drive current (all liners) vaux-v drive >0.6v 20 40 ma synchronous pwm controller error amplifier dc gain 88 db gbwp gain-bandwidth product 15 mhz sr slew rate comp=10pf 6 v/ s pwm controller gate driver i ugate ugate source v cc =12v, v ugate =6v 1 a r ugate ugate sink v ugate1-phase =1v 3.5 ? i lgate lgate source v cc =12v, v lgate =1v 1 a r lgate lgate sink v lgate = 1v 3 ?
copyright ? anpec electronics corp. rev. p.1 - mar., 2001 APW7025 www.anpec.com.tw 4 electrical characteristics cont. APW7025 symbol parameter test conditions min. typ. max. unit protection vsen1 over-voltage (vsen1/dacout) vsen1 rising 115 120 % i ovp fault souring current v fault/rt =2.0v 8.5 ma i ocset ocset current source v ocset = 4.5v dc 170 200 230 a i ss soft start current 28 a power good vsen1 upper threshold (vsen1/dacout) vsen1 rising 108 110 % vsen1 under voltage (vsen1/dacout) vsen1 rising 92 94 % vsen1 hysteresis (vsen1 /dacout) upper /lower threshold 2 % v pgood pgood voltage low i pgood = -4ma 0.8 v functional pin description vcc (pin 1) provide a 12v bias supply for the ic to this pin. this pin also provides the gate bias charge for all the mosfets controlled by the ic. the voltage at this pin is monitored for power-on reset (por) purposes. drive2 (pin 2) connect this pin to the gate of an external mosfet. this pin provides the drive for the nvvdd regulator?s pass transistor. pgood (pin 8) pgood is an open collector output used to indicate the status of the output voltages. this pin is pulled low when the synchronous regulator output is not within 10% of the dacout reference voltage or when any of the other outputs are below their under- voltage thresholds. vsen2 (pin 9) connect this pin to a resistor divider to set the linear regulator (nvvdd) output voltage. ss (pin 10) connect a capacitor from this pin to ground. this capacitor, along with an internal 28 a current source, sets the soft-start interval of the converter. fault (pin 11) this pin provides oscillator switching frequency adjustment. by placing a resistor (r t ) from this pin to gnd, the nominal 200khz switching frequency is in- creased according to the following equation: fs =200khz + 5 10 6 / r t (k ?) (r t to gnd) conversely, connecting a resistor from this pin to vcc reduces the switching frequency according to the fol- lowing equation: fs =200khz + 4 10 7 / r t (k ?) (r t to 12v) nominally, the voltage at this pin is 1.26v. in the event of an over-voltage or over-current condition, this pin
copyright ? anpec electronics corp. rev. p.1 - mar., 2001 APW7025 www.anpec.com.tw 5 is internally pulled to vcc. vaux (pin 13) this pin provides boost current for the linear regulator?s output drives in the event bipolar npn tran- sistors (instead of n-channel mosfets) are em- ployed as pass elements. the voltage at this pin is monitored for power-on reset purposes. gnd (pin 14) signal ground for the ic. all voltage levels are mea- sured with respect to this pin. drive3 (pin 15) connect this pin to the gate of an external mosfet. this pin provides the drive for the fbvddq regulator?s pass transistor. vsen3 (pin 16) connect this pin to a resistor divider to set the linear regulator (fbvddq) output voltage. comp and fb (pin 17, and 18) comp and fb are the available external pins of the pwm converter error amplifier. the fb pin is the in- verting input of the error amplifier. similarly, the comp pin is the error amplifier output. these pins are used to compensate the voltage-mode control feedback loop of the synchronous pwm converter. vsen1 (pin 19) this pin is connected to the pwm converter?s output voltage. the pgood and ovp comparator circuits use this signal to report output voltage status and for over- voltage protection. ocset (pin 20) connect a resistor from this pin to the drain of the respective upper mosfet. this resistor, an internal 200 a current source, and the upper mosfet?s on- resistance set the converter over- current trip point. an over-current trip cycles the soft- start function. the voltage at this pin is monitored for power-on re- set (por) purposes and pulling this pin low with an open drain device will shutdown the ic. pgnd (pin 21) this is the power ground connection. tie the syn- chronous pwm converter?s lower mosfet source to this pin. lgate (pin 22) connect lgate to the pwm converter?s lower mosfet gate. this pin provides the gate drive for the lower mosfet. phase (pin 23) connect the phase pin to the pwm converter?s up- per mosfet source. this pin represents the gate drive return current path and is used to monitor the voltage drop across the upper mosfet for over-cur- rent protection. ugate (pin 24) connect ugate pin to the pwm converter?s upper mosfet gate. this pin provides the gate drive for the upper mosfet. functional pin description cont.
copyright ? anpec electronics corp. rev. p.1 - mar., 2001 APW7025 www.anpec.com.tw 6 typical characteristics linear controller linear controller pwm1 controller APW7025 +5v in q1 q2 v out3 q3 v out2 +3.3v in q4 v out1 customer service anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369
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